Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel
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| 23. rida: | 23. rida: | ||
* [[Media:ITI0130_lecture3_2015.pdf|Lecture 3]]: Temporal logic CTL* | * [[Media:ITI0130_lecture3_2015.pdf|Lecture 3]]: Temporal logic CTL* | ||
* [[Media:ITI0130_lecture4_2015.pdf|Lecture 4]]: CTL model checking | * [[Media:ITI0130_lecture4_2015.pdf|Lecture 4]]: CTL model checking | ||
| + | * [[Media:ITI0130_lecture5_2015.pdf|Lecture 5]]: Timed automata and TCTL model checking | ||
==Labs== | ==Labs== | ||
Redaktsioon: 4. märts 2015, kell 11:51
Course code: ITI0130, ITI8530
Link: http://courses.cs.ttu.ee/pages/ITI0130
Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418
Previous courses: 2014
Time and place
Lectures: Wednesdays 14:00, ICT-A1
Labs: Wednesdays 16:00, ICT-401 - Evelin Halling (evelin.halling ätt ttu.ee)
News 2015
Lecture notes
- Lecture 1: Introduction to formal methods
- Lecture 2: Modelling state transition systems
- Lecture 3: Temporal logic CTL*
- Lecture 4: CTL model checking
- Lecture 5: Timed automata and TCTL model checking
Labs
- Lab 1: Introduction to modelling in UPPAAL
- UPPAAL website
- Small tutorial on UPPAAL
- Tutorial on UPPAAL
- Slides: UPPAAL introduction
- Model: Lamp example
- Query: Lamp example
- Lab 2: Introduction to modelling in UPPAAL
- Slides: Example and explanation
- Model: Coffee machine
- Query: Coffee machine
- Lab 3: Reader-Writer (unreliable) communication protocol
- Slides: Example and explanation
- Lab 4: Leader election protocol
- Slides: Explanation