Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel

Allikas: Kursused
Mine navigeerimisribale Mine otsikasti
59. rida: 59. rida:
 
== Exercises==
 
== Exercises==
 
* [[Media:Exercises1.pdf|Exercises 1]]: Model checking (explicit and symbolic state)
 
* [[Media:Exercises1.pdf|Exercises 1]]: Model checking (explicit and symbolic state)
* [[Media:DEDUCTIVE_VERIFICATION_Example_2.pdf|Exercises 2]]: Partial correctness of FOR-program (example)
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* [[Media:Exercises_2.pdf|Exercises 2a]]: Partial correctness of While-programs
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* [[Media:DEDUCTIVE_VERIFICATION_Example_2.pdf|Exercises 2b]]: Partial correctness of FOR-program (example)
  
 
==Resources==
 
==Resources==

Redaktsioon: 1. aprill 2015, kell 15:26

Course code: ITI0130, ITI8530
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Previous courses: 2014


Time and place

Lectures: Wednesdays 14:00, ICT-A1
Labs: Wednesdays 16:00, ICT-401 - Evelin Halling (evelin.halling ätt ttu.ee)

News 2015


Lecture notes

  • Lecture 1: Introduction to formal methods
  • Lecture 2: Modelling state transition systems
  • Lecture 3: Temporal logic CTL*
  • Lecture 4: CTL model checking
  • Lecture 5: Timed automata and TCTL model checking
  • Test 1: Model checking
  • Lecture 7: Program specifications
  • Lecture 8: Proving partial correctness of programs
  • Lecture 9.1: Proof techniques (1): derived rules, backwards proof, annotations
  • Lecture 9.2: Proof techniques (2): Array- and FOR-rule
  • Lecture 10: Proving total correctness of programs
  • Test 2: Deductive verification of sequential programs

Labs

Exercises

Resources