Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel

Allikas: Kursused
Mine navigeerimisribale Mine otsikasti
38. rida: 38. rida:
 
* [[Media:ITI0130_lecture9_2_2015.pdf|Lecture 12.2]]: Proof techniques (2): Array- and FOR-rule
 
* [[Media:ITI0130_lecture9_2_2015.pdf|Lecture 12.2]]: Proof techniques (2): Array- and FOR-rule
 
* [[Media:ITI0130_lecture10_2015.pdf|Lecture 13]]: Proving total correctness of while-programs  
 
* [[Media:ITI0130_lecture10_2015.pdf|Lecture 13]]: Proving total correctness of while-programs  
* Test 3 (05.05.2016): Deductive verification of sequential programs
+
* [[Media:ITI0130_lecture11_2015nondeterministic.pdf|Lecture 15]]: Verifying nondeterministic and
* [[Media:ITI0130_lecture11_2015nondeterministic.pdf|Lecture 15]]: Non-deterministic programs
 
* [[Media:ITI0130_lecture_12_2015.pdf|Lecture 16]]: Parallel programs with shared variables
 
* [[Media:ITI0130_lecture_13_2015.pdf|Lecture 17]]: Parallel programs with message passing
 
* [[Media:ITI8531_lecture_14_2016.pdf|Lecture 18]]: Program synthesis
 
 
* Test 3 (26.05.2016): Deductive verification of non-deterministic and parallel programs
 
* Test 3 (26.05.2016): Deductive verification of non-deterministic and parallel programs
  

Redaktsioon: 11. mai 2017, kell 06:54

Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Lab assistants: Evelin Halling, Jishu Quin
Contact: evelin.halling ätt ttu.ee,


Previous courses: 2014


Time and place

Lectures: Thursdays 10:00, ICT-A2
Labs: Thursdays 12:00, ICT-402 - Evelin Halling, Jishu Quin // Lab on March 16 will be cancelled due to the sickness of lab instructor..

Lecture plan

  • Lecture 1: Introduction
  • Lecture 2: Modelling state transition systems
  • Lecture 3: Temporal logic CTL*
  • Lecture 4: CTL model checking
  • Lecture 5: Timed automata and TCTL model checking
  • Practicing for Test 1 (see Exercises 1 below)
  • Test 1: Model checking (16.03.2017)
  • Lecture 7: Program specifications
  • Lecture 8: Program synthesis I
  • Lecture 9: Program synthesis II
  • Test 2 (13.04.2017): Program synthesis
  • Lecture 11: Proving partial correctness of programs
  • Lecture 12.1: Proof techniques (1): derived rules, backwards proof, annotations
  • Lecture 12.2: Proof techniques (2): Array- and FOR-rule
  • Lecture 13: Proving total correctness of while-programs
  • Lecture 15: Verifying nondeterministic and
  • Test 3 (26.05.2016): Deductive verification of non-deterministic and parallel programs

Labs


Exercises

  • Exercises 1: Model checking (explicit and symbolic state)
  • Exercises 2: Partial correctness of WHILE-programs
  • Partial correctness of non-deterministic and parallel programs
    • Exercises 3.1: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.2: Partial correctness of non-deterministic and parallel programs NEW!!!

Resources