Software Synthesis and Verification

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Redaktsioon seisuga 31. mai 2017, kell 07:23 kasutajalt Vain (arutelu | kaastöö) (→‎Time and place)
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Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Lab assistants: Evelin Halling, Jishu Quin
Contact: evelin.halling ätt ttu.ee,


Previous courses: 2014


Time and place

Lectures: Thursdays 10:00, ICT-A2
Labs: Thursdays 12:00, ICT-402 - Evelin Halling, Jishu Quin

New! Exams: Thursday May 1, 10:00, room ICT-A1 Thursday May 8, 10:00, room ICT-A1

Lecture plan

  • Lecture 1: Introduction
  • Lecture 2: Modelling state transition systems
  • Lecture 3: Temporal logic CTL*
  • Lecture 4: CTL model checking
  • Lecture 5: Timed automata and TCTL model checking
  • Practicing for Test 1 (see Exercises 1 below)
  • Test 1: Model checking (16.03.2017)
  • Lecture 7: Program specifications
  • Lecture 8: Program synthesis I
  • Lecture 9: Program synthesis II
  • Test 2 (13.04.2017): Program synthesis
  • Lecture 11: Proving partial correctness of programs
  • Lecture 12.1: Proof techniques (1): derived rules, backwards proof, annotations
  • Lecture 12.2: Proof techniques (2): Array- and FOR-rule
  • Lecture 13: Proving total correctness of while-programs
  • Lecture 14: Verifying nondeterministic and parallel programs
  • Test 3 (25.05.2017): Deductive verification of non-deterministic and parallel programs

Labs


Exercises

  • Exercises 1: Model checking (explicit and symbolic state)
  • Exercises 2: Partial correctness of WHILE-programs
  • Partial correctness of non-deterministic and parallel programs
    • Exercises 3.1: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.2: Partial correctness of non-deterministic and parallel programs NEW!!!

Resources