Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel

Allikas: Kursused
Mine navigeerimisribale Mine otsikasti
 
(ei näidata 4 kasutaja 70 vahepealset redaktsiooni)
4. rida: 4. rida:
 
'''Lecturer''': prof. Jüri Vain <br>
 
'''Lecturer''': prof. Jüri Vain <br>
 
'''Contact''': juri.vain ätt ttu.ee, ICT-418 <br>
 
'''Contact''': juri.vain ätt ttu.ee, ICT-418 <br>
 +
 +
<!-- '''Lecturer''': Leonidas Tsiopoulos <br>
 +
'''Contact''': leonidas.tsiopoulos ätt ttu.ee, ICT-418 <br>
 +
 +
'''Lecturer''': Maksym Bortin <br>
 +
'''Contact''': maksym.bortin ätt ttu.ee, room B404 in the Cybernetics Building <br>
  
 
'''Lab assistant''':  
 
'''Lab assistant''':  
Deepak Pal <br>
+
Evelin Halling <br>
'''Contact''': deepak.pal ätt ttu.ee, <br>
+
'''Contact''': evelin.halling ätt ttu.ee <br>
 
+
-->
  
  
17. rida: 23. rida:
 
==Time and place==
 
==Time and place==
  
Lectures: Thursdays 10:00, ICT-A1 <br>
+
Lectures: Thursdays 10:00, ICT-315 <br>
Labs: Thursdays 12:00, ICT-122 - Deepak Pal
+
Labs: Thursdays 12:00, ICT-404 - Jüri Vain
  
 
'''New!'''<br>
 
'''New!'''<br>
'''Exams: '''
+
* Due to CORONA restrictions course is entirely running over Teams channel "Software synthesis and Verification"
* Thursday May 1, 10:00, room ICT-A2 <br>
+
'''Exams: (To Be Updated) '''
* Thursday May 8, 10:00, room ICT-A2'''
+
* ... <br>
 +
** Exam is for those who have not passed any of the tests or want to improve their final mark
 +
<!--* ... '''
 +
 
 +
-->
  
==Lecture plan==
+
==Lecture plan - To be updated for Module II and III==
 
* [[Media:ITI8531_Lecture_1_18_Intro.pdf|Lecture 1]]: Introduction
 
* [[Media:ITI8531_Lecture_1_18_Intro.pdf|Lecture 1]]: Introduction
* [[Media:ITI8531_Lecture_2_18_transition_systems.pdf|Lecture 2]]: Modelling state transition systems
+
* [[Media:ITI8531_Lecture_2_2022_transition_systems.pdf|Lecture 2]]: Modelling state transition systems
* [[Media:ITI8531_Lecture_3_18_CTL.pdf|Lecture 3]]: Temporal logic CTL*
+
* [[Media:ITI8531_Lecture_3_2022_CTL.pdf|Lecture 3]]: Temporal logic CTL*
 
* [[Media:ITI8531_Lecture_4_18_modelchecking.pdf|Lecture 4]]: CTL model checking
 
* [[Media:ITI8531_Lecture_4_18_modelchecking.pdf|Lecture 4]]: CTL model checking
* [[Media:ITI8531_Lecture_5_18_TA_and_TCTL.pdf|Lecture 5]]: Timed automata and TCTL model checking
+
* [[Media:ITI8531_Lecture_5_22_symb_modelchecking.pdf|Lecture 5]]: Symbolic model checking
* Practicing for Test 1 (see Exercises 1 below)
+
* [[Media:ITI8531_Lecture_6_22_TA_and_TCTL.pdf|Lecture 6]]: Model checking TCTL
* Test 1: Model checking ('''16.03.2017''')
+
* Practicing for Test 1: Model checking  [[Media:ITI8531_Exercises_1_2016.pdf|Exercises]]: (05.03.2019)
** [[Media:ITI8531_Exercises_1_2016.pdf|Exercises]]: Model checking
+
* Test 1: Model checking ('''12.03.2019''')
* [[Media:ITI8531_Lecture_5_16_Specifications.pdf|Lecture 7]]: Program specifications
+
* [[Media:ITI8531_Lecture_6.1_18_Specifications.pdf|Lecture 6]]: Program specifications (19.03.2019)
* [[Media:ITI8531_synthesis1_2017.pdf|Lecture 8]]: Program synthesis I
+
* [[Media:ITI8531_Lecture_6.2_18_verification.pdf|Lecture 7]]: Proving partial correctness of programs (19.03.2019)
* [[Media:ITI8531_synthesis2_2017.pdf|Lecture 9]]: Program synthesis II
+
* [[Media:ITI8531_Lecture_7_18_proving (2).pdf|Lecture 8]]: Proof techniques (1): derived rules, backwards proof, annotations (26.03.2019)
* Test 2 (13.04.2017): Program synthesis
+
* [[Media:ITI8531_Lecture_8_18_total_correctness.pdf|Lecture 9]]: Proving total correctness of while-programs (26.03.2019)
* [[Media:ITI8531_Lecture_6_16_rules.pdf|Lecture 11]]: Proving partial correctness of programs
+
* [[Media:ITI8531_Lecture_9_2017_parallel_programs.pdf|Lecture 10]]: Verifying nondeterministic and parallel programs  (02.04.2019)
* [[Media:ITI0130_lecture9_1_2015.pdf|Lecture 12.1]]: Proof techniques (1): derived rules, backwards proof, annotations
+
* Practicing for Test 2: Deductive verification of non-deterministic and parallel programs (04.04.2019 at lab time)
* [[Media:ITI0130_lecture9_2_2015.pdf|Lecture 12.2]]: Proof techniques (2): Array- and FOR-rule
+
** [[Media:ITI8531_Genzen_1st_order_calculus.pdf|Genzen 1st order calculus]]: Genzen 1st order sequent calculus (proof rules)
* [[Media:ITI0130_lecture10_2015.pdf|Lecture 13]]: Proving total correctness of while-programs
+
* Test 2: Deductive verification of sequential, non-deterministic and parallel programs ('''09.04.2019,at 12.00''')
* [[Media:ITI8531_Lecture_9_2017_parallel_programs.pdf|Lecture 14]]: Verifying nondeterministic and parallel programs
+
* [[Media:Software Synthesis - Overview of Temporal Synthesis - Lecture 11.pdf|Lecture 11]]: Software synthesis I (16.04.2019)
* Test 3 (25.05.2017): Deductive verification of non-deterministic and parallel programs
+
* [[Media:Software Synthesis - Introduction to Acacia - Lecture 12.pdf|Lecture 12]]: Software synthesis II (23.04.2019)
 +
* [[Media:Software Synthesis - LTL Synthesis and Acacia II - Lecture 13.pdf|Lecture 13]]: Software synthesis III (30.04.2019)
 +
* [[Media:Software Synthesis - LTL Synthesis with Acacia part III - Lecture 14.pdf|Lecture 14]]: Software synthesis IV (7.05.2019)
 +
* [[Media:Software Synthesis - Lecture V - Recap.pdf|Lecture 15]]: Software synthesis (recap) and practicing for test  (14.05.2019)
 +
* Test 3: Software synthesis ('''16.05.2019''')
 +
* Retake of Test 2, 2nd task: ('''21.05.2019 at 12.00 (New!)''')
 +
** [[Media:Test_2_2019_lahendus.pdf|Eample_Solution]]: ('''Example solution of Task2 (NEW!)''')
  
==Labs==
+
==Labs - To be updated from lab 4 onwards==
 +
* Exercise Environment for Module II:
 +
** Download and install the environment: [[Media:HoareLogic.tar| Hoare Logic environment]]
 
* Lab 1: Introduction to modelling in UPPAAL  
 
* Lab 1: Introduction to modelling in UPPAAL  
 
** Slides: [[Media:UPPAAL Tutorial.pdf|UPPAAL introduction]]
 
** Slides: [[Media:UPPAAL Tutorial.pdf|UPPAAL introduction]]
65. rida: 83. rida:
 
** Query: [[Media:Jobber_Query1.q|JobShop Query]]
 
** Query: [[Media:Jobber_Query1.q|JobShop Query]]
  
 +
* Lab 4: Assignment I: Reader-Writer (unreliable) communication protocol
 +
** Slides: [[Media:ITI0130_Lab2_2015.pdf|Example and explanation]]
 +
 +
* Lab 5: Assignment II: Leader election protocol
 +
** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]]
 +
** [http://perso.ens-lyon.fr/pierre.lescanne/ENSEIGNEMENT/REECRITURE/ABRIAL/sldp.ieee1394.pdf The Leader Election Protocol (IEEE 1394)]
 +
** [http://link.springer.com/article/10.1023%2FA%3A1008764923992 Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394]
 +
** Reference solution: [[Media:FASDS.pdf|Chapter 12, page 172]]
 +
 +
* Lab 13:
 +
** [http://web.iitd.ac.in/~sumeet/slide3.pdf LTL]
 +
* Lab 14:
 +
** [[Media:ITI8531_LTL_exercises.pdf|Exercises]]
 +
** [http://goal.im.ntu.edu.tw/wiki/doku.php GOAL tool]
 +
** [http://www.lsv.fr/~gastin/ltl2ba/ LTL2BA]
 +
* Lab 15
 +
** [[Media:ITI8531_LTL_assignments.pdf|LTL Assignment]]
 +
** [[Media:Software Synthesis and Verification LTL Assignment-Updated Spec.pdf|Updated Spec for LTL Synthesis Assignment]]
 +
** [[Media:Guidelines for Lab Exercise Report for Synthesis with Acacia.pdf|Guidelines for Assignment]]
 +
** [[Media:Acacia Installation Commands.pdf|Acacia Tool Installation Commands]]
 +
** [[Media:Acacia_Manual.pdf|Acacia Tool Installation Guidelines and Manual for Command Line Options]]
 +
 +
<!--
 
* Lab 4-5: Implementation of Mutual Exclusion Algorithms in UPPAAL  
 
* Lab 4-5: Implementation of Mutual Exclusion Algorithms in UPPAAL  
 
** Slides: [[Media:Lecture_5.pdf|The Mutual Exclusion Problem and Algorithms]]
 
** Slides: [[Media:Lecture_5.pdf|The Mutual Exclusion Problem and Algorithms]]
75. rida: 116. rida:
 
* Lab 7-8: Assignment: Reader-Writer (unreliable) communication protocol
 
* Lab 7-8: Assignment: Reader-Writer (unreliable) communication protocol
 
** Slides: [[Media:ITI0130_Lab2_2015.pdf|Example and explanation]]
 
** Slides: [[Media:ITI0130_Lab2_2015.pdf|Example and explanation]]
 +
 +
* Lab 9: Assignment: Elevator Control
 +
** Slides: [[Media:ElevatorControl_V1_29062017.pdf|Example and explanation]]
 +
** Slides: [[Media:ModellingRequirement.pptx|Modelling Requirements]]
 +
 +
* Lab 10: Final Assessment on 17 May 2018
 +
** Lab defending of all given assignment.
 +
-->
  
 
<!--
 
<!--
81. rida: 130. rida:
 
** Model: [[Media:ITI0130_Coffee.xml|Coffee machine]]
 
** Model: [[Media:ITI0130_Coffee.xml|Coffee machine]]
 
** Query: [[Media:ITI0130_Coffee.q|Coffee machine]]
 
** Query: [[Media:ITI0130_Coffee.q|Coffee machine]]
 +
 
* Lab 6: Assignment 3: Leader election protocol  
 
* Lab 6: Assignment 3: Leader election protocol  
 
** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]]
 
** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]]

Viimane redaktsioon: 9. veebruar 2023, kell 09:58

Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418


Previous courses: 2014


Time and place

Lectures: Thursdays 10:00, ICT-315
Labs: Thursdays 12:00, ICT-404 - Jüri Vain

New!

  • Due to CORONA restrictions course is entirely running over Teams channel "Software synthesis and Verification"

Exams: (To Be Updated)

  • ...
    • Exam is for those who have not passed any of the tests or want to improve their final mark

Lecture plan - To be updated for Module II and III

  • Lecture 1: Introduction
  • Lecture 2: Modelling state transition systems
  • Lecture 3: Temporal logic CTL*
  • Lecture 4: CTL model checking
  • Lecture 5: Symbolic model checking
  • Lecture 6: Model checking TCTL
  • Practicing for Test 1: Model checking Exercises: (05.03.2019)
  • Test 1: Model checking (12.03.2019)
  • Lecture 6: Program specifications (19.03.2019)
  • Lecture 7: Proving partial correctness of programs (19.03.2019)
  • Lecture 8: Proof techniques (1): derived rules, backwards proof, annotations (26.03.2019)
  • Lecture 9: Proving total correctness of while-programs (26.03.2019)
  • Lecture 10: Verifying nondeterministic and parallel programs (02.04.2019)
  • Practicing for Test 2: Deductive verification of non-deterministic and parallel programs (04.04.2019 at lab time)
  • Test 2: Deductive verification of sequential, non-deterministic and parallel programs (09.04.2019,at 12.00)
  • Lecture 11: Software synthesis I (16.04.2019)
  • Lecture 12: Software synthesis II (23.04.2019)
  • Lecture 13: Software synthesis III (30.04.2019)
  • Lecture 14: Software synthesis IV (7.05.2019)
  • Lecture 15: Software synthesis (recap) and practicing for test (14.05.2019)
  • Test 3: Software synthesis (16.05.2019)
  • Retake of Test 2, 2nd task: (21.05.2019 at 12.00 (New!))

Labs - To be updated from lab 4 onwards


Exercises

  • Exercises 1: Model checking (explicit and symbolic state)
  • Exercises 2: Partial correctness of WHILE-programs
  • Partial correctness of non-deterministic and parallel programs
    • Exercises 3.1: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.2: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.3: Parallel programs with message passing

Resources