Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel

Allikas: Kursused
Mine navigeerimisribale Mine otsikasti
64. rida: 64. rida:
 
** Installation: [[Media:ITI0130_Lab7_2016_KeY.pdf|KeY Installation]]
 
** Installation: [[Media:ITI0130_Lab7_2016_KeY.pdf|KeY Installation]]
 
** Bank example: [[Media:ITI0130_Lab7_2016_Bank.zip|Bank example]]
 
** Bank example: [[Media:ITI0130_Lab7_2016_Bank.zip|Bank example]]
 +
** Bank JML: [[Media:ITI0130_Lab7_2016_Bank_JML.zip|Bank JML]]
  
 
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Redaktsioon: 14. aprill 2016, kell 07:57

Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Previous courses: 2014


Time and place

Lectures: Thursdays 12:00, ICT-A1
Labs: Thursdays 10:00, ICT-405 - Evelin Halling (evelin.halling ätt ttu.ee)

News 2016

  • Written exam I: at 14.00 on May 27, Room ICT-411
  • Written exam II: at 14.00 on June 3, Room ICT-411


Lecture plan

  • Lecture 1: Introduction
  • Lecture 2: Modelling state transition systems
  • Lecture 3: Temporal logic CTL*
  • Lecture 4: CTL model checking
  • Lecture 5: Timed automata and TCTL model checking
  • Test 1: Model checking
  • Lecture 7: Program specifications
  • Lecture 8: Proving partial correctness of programs
  • Lecture 9.1: Proof techniques (1): derived rules, backwards proof, annotations
  • Lecture 9.2: Proof techniques (2): Array- and FOR-rule
  • Lecture 10: Proving total correctness of while-programs
  • Test 2: Deductive verification of sequential programs
  • Lecture 11: Non-deterministic programs
  • Lecture 12: Parallel programs with shared variables
  • Lecture 13: Parallel programs with message passing
  • Test 3: Deductive verification of non-deterministic and parallel programs

Labs


Exercises

  • Exercises 1: Model checking (explicit and symbolic state)
  • Exercises 2: Partial correctness of WHILE-programs
  • Exercises 3: Partial correctness of non-deterministic and parallel programs

Resources