Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel

Redaktsioon: 22. veebruar 2018, kell 07:08

Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Lab assistant: Deepak Pal
Contact: deepak.pal ätt ttu.ee,

Previous courses: 2014

Lectures: Thursdays 10:00, ICT-A1
Labs: Thursdays 12:00, ICT-122 - Deepak Pal

New!
Exams:

Lecture 1: Introduction
Lecture 2: Modelling state transition systems
Lecture 3: Temporal logic CTL*
Lecture 4: CTL model checking
Lecture 5: Timed automata and TCTL model checking
Practicing for Test 1 (see Exercises 1 below)
Test 1: Model checking (16.03.2017)
- Exercises: Model checking
Lecture 7: Program specifications
Lecture 8: Program synthesis I
Lecture 9: Program synthesis II
Test 2 (13.04.2017): Program synthesis
Lecture 11: Proving partial correctness of programs
Lecture 12.1: Proof techniques (1): derived rules, backwards proof, annotations
Lecture 12.2: Proof techniques (2): Array- and FOR-rule
Lecture 13: Proving total correctness of while-programs
Lecture 14: Verifying nondeterministic and parallel programs
Test 3 (25.05.2017): Deductive verification of non-deterministic and parallel programs

Lab 2: Validation (simulation) and verification (automatic model-checking) in UPPAAL
- Slides: Model Checking introduction
- Model: ATM System Model
- Query: ATM System Query

Lab 3: Understanding of Clocks and State Space Explosion in UPPAAL
- Slides: Model Checking introduction
- Model: ATM System Model
- Query: ATM System Query

Lab 4: Assignment 1: Coffee Machine
- Slides: Example and explanation
- Model: Coffee machine
- Query: Coffee machine
Lab 5: Assignment 2: Reader-Writer (unreliable) communication protocol
- Slides: Example and explanation
Lab 6: Assignment 3: Leader election protocol
- Slides: Explanation
- The Leader Election Protocol (IEEE 1394)
- Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394
- Reference solution: Chapter 12
Lab 7: Lab Exam
- Homework defenses

Exercises 1: Model checking (explicit and symbolic state)
Exercises 2: Partial correctness of WHILE-programs
- Example 1: Partial correctness of WHILE-loop
- Example 2: Partial correctness of FOR-loop
Partial correctness of non-deterministic and parallel programs
- Exercises 3.1: Partial correctness of non-deterministic and parallel programs
- Exercises 3.2: Partial correctness of non-deterministic and parallel programs
- Exercises 3.3: Parallel programs with message passing

@@ 60. rida: / 60. rida: @@
 ** Query: [[Media:Atm_system_query.q|ATM System Query]]
-* Lab 3: Assignment 1: Coffee Machine
+* Lab 3: Understanding of Clocks and State Space Explosion in UPPAAL
+** Slides: [[Media:New_Lab2_MODEL_CHECKING.pdf|Model Checking introduction]]
+** Model: [[Media:Atm_system.xml|ATM System Model]]
+** Query: [[Media:Atm_system_query.q|ATM System Query]]
+* Lab 4: Assignment 1: Coffee Machine
 ** Slides: [[Media:ITI0130_Lab1_Coffee_machine_2015.pdf|Example and explanation]]
 ** Model: [[Media:ITI0130_Coffee.xml|Coffee machine]]
 ** Query: [[Media:ITI0130_Coffee.q|Coffee machine]]
-* Lab 4: Assignment 2: Reader-Writer (unreliable) communication protocol
+* Lab 5: Assignment 2: Reader-Writer (unreliable) communication protocol
 ** Slides: [[Media:ITI0130_Lab2_2015.pdf|Example and explanation]]
-* Lab 5: Assignment 3: Leader election protocol
+* Lab 6: Assignment 3: Leader election protocol
 ** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]]
 ** [http://perso.ens-lyon.fr/pierre.lescanne/ENSEIGNEMENT/REECRITURE/ABRIAL/sldp.ieee1394.pdf The Leader Election Protocol (IEEE 1394)]
 ** [http://link.springer.com/article/10.1023%2FA%3A1008764923992 Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394]
 ** Reference solution: [[Media:FASDS.pdf|Chapter 12]]
-* Lab 6: Lab Exam
+* Lab 7: Lab Exam
 ** Homework defenses