Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel

Allikas: Kursused
Mine navigeerimisribale Mine otsikasti
66. rida: 66. rida:
 
** Query: [[Media:Jobber_Query1.q|JobShop Query]]
 
** Query: [[Media:Jobber_Query1.q|JobShop Query]]
  
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* Lab 4: Assignment I: Reader-Writer (unreliable) communication protocol
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** Slides: [[Media:ITI0130_Lab2_2015.pdf|Example and explanation]]
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* Lab 5: Assignment II: Leader election protocol
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** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]]
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** [http://perso.ens-lyon.fr/pierre.lescanne/ENSEIGNEMENT/REECRITURE/ABRIAL/sldp.ieee1394.pdf The Leader Election Protocol (IEEE 1394)]
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** [http://link.springer.com/article/10.1023%2FA%3A1008764923992 Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394]
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** Reference solution: [[Media:FASDS.pdf|Chapter 12]]
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* Lab 4-5: Implementation of Mutual Exclusion Algorithms in UPPAAL  
 
* Lab 4-5: Implementation of Mutual Exclusion Algorithms in UPPAAL  
 
** Slides: [[Media:Lecture_5.pdf|The Mutual Exclusion Problem and Algorithms]]
 
** Slides: [[Media:Lecture_5.pdf|The Mutual Exclusion Problem and Algorithms]]
83. rida: 93. rida:
 
* Lab 10: Final Assessment on 17 May 2018
 
* Lab 10: Final Assessment on 17 May 2018
 
** Lab defending of all given assignment.
 
** Lab defending of all given assignment.
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Redaktsioon: 28. veebruar 2019, kell 07:31

Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Lab assistant: Evelin Halling
Contact: evelin.halling ätt ttu.ee,


Previous courses: 2014


Time and place

Lectures: Tuesdays 12:00, ICT-A1
Labs: Thursdays 10:00, ICT-A1 - Evelin Halling

New!
Exams:

  • Thursday May 24, 10:00, room ICT-A1
  • Thursday May 31, 10:00, room ICT-A1

Lecture plan

  • Lecture 1: Introduction
  • Lecture 2: Modelling state transition systems
  • Lecture 3: Temporal logic CTL*
  • Lecture 4: CTL model checking
  • Lecture 5: Timed automata and TCTL model checking
  • Practicing for Test 1 (see Exercises 1 below)
  • Test 1: Model checking (15.03.2018)
  • Lecture 7.1: Program specifications
  • Lecture 7.2: Proving partial correctness of programs
  • Lecture 8: Proof techniques (1): derived rules, backwards proof, annotations
  • Lecture 9: Proving total correctness of while-programs
  • Lecture 14: Verifying nondeterministic and parallel programs
  • Practicing for Test 2 (26.04.2018): Deductive verification of non-deterministic and parallel programs
  • Test 2 (03.05.2018, 12.00): Deductive verification of sequential, non-deterministic and parallel programs
  • Lecture 8: Program synthesis I
  • Lecture 9: Program synthesis II
  • Repetition of test 1 and test 2 (17.05.2018)

Labs


Exercises

  • Exercises 1: Model checking (explicit and symbolic state)
  • Exercises 2: Partial correctness of WHILE-programs
  • Partial correctness of non-deterministic and parallel programs
    • Exercises 3.1: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.2: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.3: Parallel programs with message passing

Resources