Software Synthesis and Verification

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Redaktsioon seisuga 3. mai 2018, kell 06:44 kasutajalt Vain (arutelu | kaastöö) (→‎Lecture plan)
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Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Lab assistant: Deepak Pal
Contact: deepak.pal ätt ttu.ee,


Previous courses: 2014


Time and place

Lectures: Thursdays 10:00, ICT-A1
Labs: Thursdays 12:00, ICT-122 - Deepak Pal

New!
Exams:

  • Thursday May 1, 10:00, room ICT-A2
  • Thursday May 8, 10:00, room ICT-A2

Lecture plan

  • Lecture 1: Introduction
  • Lecture 2: Modelling state transition systems
  • Lecture 3: Temporal logic CTL*
  • Lecture 4: CTL model checking
  • Lecture 5: Timed automata and TCTL model checking
  • Practicing for Test 1 (see Exercises 1 below)
  • Test 1: Model checking (15.03.2018)
  • Lecture 7.1: Program specifications
  • Lecture 7.2: Proving partial correctness of programs
  • Lecture 8: Proof techniques (1): derived rules, backwards proof, annotations
  • Lecture 9: Proving total correctness of while-programs
  • Lecture 14: Verifying nondeterministic and parallel programs
  • Practicing for Test 2 (26.04.2018): Deductive verification of non-deterministic and parallel programs
  • Test 2 (03.05.2018, 12.00): Deductive verification of sequential, non-deterministic and parallel programs
  • Lecture 8: Program synthesis I
  • Lecture 9: Program synthesis II
  • Test 3 (13.04.2017): Program synthesis

Labs

  • Lab 6: Lab Assignment: ATM System, JobShop, Implementation of Mutual Exclusion Algo.


Exercises

  • Exercises 1: Model checking (explicit and symbolic state)
  • Exercises 2: Partial correctness of WHILE-programs
  • Partial correctness of non-deterministic and parallel programs
    • Exercises 3.1: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.2: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.3: Parallel programs with message passing

Resources